`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/09 16:45:58
// Design Name: 
// Module Name: flowlight_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module flowLED_top_sim();
    reg clk = 0;
    reg rst_n_i = 1;
    reg en_i = 1;
    wire [7:0] led_o;
    
    flowLED_top UUT(.rst_n_i(rst_n_i), .clk_i(clk), .en_i(en_i), .led_o(led_o));
    
    always #1 begin clk = ~clk; end
    
    initial begin
        #30 en_i = 0;
        #30 en_i = 1;
        #20 rst_n_i = 0;
        #40 rst_n_i = 1;
        #50 $stop;
    end
endmodule
